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publication number s72ws-n_00 revision a amendment 9 issue date may 8, 2007 s72ws-n based mcp/pop products s72ws-n based mcp/pop products cover sheet 1.8 volt-only x16 flash memo ry and sdram on split bus 256/512 mb simultaneous read/writ e, burst mode flash memory 512 mb nand flash 1024 mb nand inte rface ornand flash me mory on bus 1 512/256/128 mb (8m/4m/2m x 16-bit x 4 banks) mobi le sdram on bus 2 data sheet (advance information) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document contains information on one or more products under development at spansion inc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed pr oduct without notice. publication number s72ws-n_00 revision a amendment 9 issue date may 8, 2007 features ? power supply voltage of 1.7 to 1.95v high performance ? flash access time: 80 ns for nor flash, 25 ns for ornand flash ? flash burst frequencies: 54 mhz, 66mhz, 80mhz ? mobile sdram burst frequency: 104 mhz, 133 mhz (ddr) ? package: ? 9.0 x 12.0 mm mcp bga ? 11.0 x 13.0 mm mcp bga ? 15.0 x 15.0 x 1.2 mm mcp package-on-package (pop) ? operating temperature ? ?25c to +85c (wireless) general description the s72ws series is a product line of stacked mult i-chip product (mcp) packages and consists of: ? one or two nor flash memory dies ? one nand interface ornand die ? separate bus for one or more mobile sdram die the products covered by this document are listed in the table below. note for a list of pop opns, please contact the local sales representative or refer to the valid combinations tables. for detailed specifications, please re fer to the individual data sheets. s72ws-n based mcp/pop products 1.8 volt-only x16 flash memo ry and sdram on split bus 256/512 mb simultaneous read/writ e, burst mode flash memory 512 mb nand flash 1024 mb nand inte rface ornand flash me mory on bus 1 512/256/128 mb (8m/4m/2m x 16-bit x 4 banks) mobi le sdram on bus 2 data sheet (advance information) device nor flash density nand flash density sdram density 512mb 256mb 128mb 1024mb 512mb 512mb 256mb 128mb s72ws256nd0 x x s72ws256nde x x s72ws256nee x x s72ws512nfg x x x s72ws512neg x x x s72ws512nef x x x s72ws512nff x x x document publication identification number (pid) s29ws256n s29ws-n_00 s30ms01gp/512p s30ms-p_00 128 mb mobile sdram type 1 sdram_01 128 mb mobile sdram type 2 sdram_05 128 mb mobile ddr-dram type 5 sdram_07 256 mb mobile sdram type 2 sdram_05 512 mb mobile ddr-dram type 1 sdram_09 512 mb mobile sdram type 4 sdram_06 512 mb nand type 1 nand_01 512 mb mobile ddr-dram type 5 dram_04 512 mb mobile ddr-dram type 2 dram_05
4 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 nor flash + dram products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 nor flash + ornand flash + dram products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 nor flash + ornand flash + dram products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 2 x 256mb nor flash with 256mb sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 2 x 256mb nor flash with 128mb sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 256mb nor flash with 128mb sdr/ddr-dram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 512 mb nor flash with 1024-mb ornand on bus 1 and 512 or 256-mb sdram on bus 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 512mb nor flash with 1024-mb ornand on bus 1 and 512 or 256 mb sdram on bus 2 12 3.6 512mb nor flash with 512-mb nand on bus 1 and 512-mb sdram on bus 2. . . . . . . . . 13 3.7 lookahead diagram on split bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 nor flash and dram input/output descr iptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 5 data sheet (advance information) 1. product selector guide 1.1 nor flash + dram products device-model# flash density (code) flash density (data) burst speed (mhz) sdram density sdram burst speed (mhz) dram supplier dyb package s72ws256nd0bawb7 256 mb ? 54 mhz 128 104 mhz 1 sector unprotected 9x12x1.2 s72ws256nd0bawbb 2 s72ws256ndebawu7 256 mb 256 mb 54 mhz 128 104 mhz 1 sector unprotected 9x12x1.4 s72ws256ndebawub 2 s72ws256neebawu7 256 1 s72ws256neebawub 2 s72ws256nd0bfwb7 256 mb ? 54 mhz 128 104 mhz 1 sector unprotected 9x12x1.2 s72ws256nd0bfwbb 2 s72ws256ndebfwu7 256 mb 256 mb 54 mhz 128 104 mhz 1 sector unprotected 9x12x1.4 s72ws256ndebfwub 2 s72ws256neebfwu7 256 1 s72ws256neebfwub 2 s72ws256nd0kfwd3 256 mb 66 mhz 128 133 mhz (ddr) 5 sector unprotected 15x15x1.25 s72ws256nd0bfw93 133 mhz (ddr) sector unprotected 9x12x1.2
6 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) 1.2 nor flash + ornand flash + dram products device-model# nor flash density ornand flash density sdram density flash speed dram speed supplier ornand bus width ecc required? package s72ws512nffbfwz2 512 mb 512 mb (nand) 512 mb 66 mhz 133 mhz (ddr) dram type 1 x16 yes 11x13x1.4 mm s72ws512nffbfwzj dram type 5 s72ws512nfg-l7 1024mb 54 mhz 104 mhz dram type 4 no 11x13x1.4 mm s72ws512nfg-l6 66 mhz s72ws512nfg-l5 80 mhz s72ws512nfg-47 54 mhz x8 s72ws512nfg-46 66 mhz s72ws512nfg-45 80 mhz s72ws512nfg-lz 54 mhz dram type 2 x16 s72ws512nfg-ly 66 mhz s72ws512nfg-lw 80 mhz s72ws512nfg-4z 54 mhz x8 s72ws512nfg-4y 66 mhz s72ws512nfg-4w 80 mhz s72ws512nfg-n7 54 mhz dram type 4 x16 ye s s72ws512nfg-n6 66 mhz s72ws512nfg-n5 80 mhz s72ws512nfg-67 54 mhz x8 s72ws512nfg-66 66 mhz s72ws512nfg-65 80 mhz s72ws512nfg-nz 54 mhz dram type 2 x16 s72ws512nfg-ny 66 mhz s72ws512nfg-nw 80 mhz s72ws512nfg-6z 54 mhz x8 s72ws512nfg-6y 66 mhz s72ws512nfg-6w 80 mhz s72ws512neg-lz 256 mb 54 mhz x16 no s72ws512neg-ly 66 mhz s72ws512neg-lw 80 mhz s72ws512neg-4z 54 mhz x8 s72ws512neg-4y 66 mhz s72ws512neg-4w 80 mhz s72ws512neg-nz 54 mhz x16 ye s s72ws512neg-ny 66 mhz s72ws512neg-nw 80 mhz s72ws512neg-6z 54 mhz x8 s72ws512neg-6y 66 mhz s72ws512neg-6w 80 mhz s72ws512nefkfwhj 512 mb 512 mb (nand) 256 mb 66 mhz 133 mhz (ddr) dram type2 x16 yes 15x15x1.25 mm s72ws512nffkfwz2 512 mb dram type 1 15x15x1.25 mm s72ws512nffkfwzj dram type 5 15x15x1.25 mm
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 7 data sheet (advance information) 2. mcp block diagram 2.1 nor flash + ornand flash + dram products notes 1. for a one-flash configuration, f1-ce# = ce#. for a two-flash configuration, f1-ce# = ce for flash 1 and f2-ce# = ce for flash 2; f2-ce# is the chip-enable pin for the secon d flash. 2. if ornand is not present in the mcp, then the ms01gp block will not be present in the figure above. in that case, the common signals go only to the ws256n flash, while the sdram signals remain unchanged. 3. if ornand supports a x16 bus, then nor dq0-dq15 is shared with ornand i/o0-i/o15. dq0:7 dq0:15 dq0:7 a23-a0 f-a23:a0 a12-a0 oe# ce# f-oe# we# f-we# ce# f1-ce# ws256n we# ba0 ras# cke cas# sdram dm0 dm1 rdy rdy reset# f-reset# wp# f-wp# ms01gp io0:7 ry/by# ry/by# re# we# n-re# ce# n-we# n-ce# wp# n-wp# ale n-ale cle n-cle f-vcc d-vcc n-vcc f2-ce# pre n-pre ce# v-vccq ba1 d-a12-a0 d-ce# d-we# d-ba0 d-ras# d-cke d-cas# d-dm0 d-dm1 d-ba1 vss vss d-vss d-vssq d-dq15-dq0 acc f-acc f-clk f-avd# clk avd# dq8:15 dq8:15 f-vccq
8 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) 3. connection diagram 3.1 2 x 256mb nor flash with 256mb sdram note m8 is rfu for sdr-dram and f-v ccq for ddr-dram, as indicated in subsequent connection diagrams. sdram only legend reserved fo r future use a1 a10 b4 b7 b8 b9 b3 b2 b6 a2 a3 a4 a5 a6 a7 a8 a9 b5 b1 b10 c4 c7 c8 c9 c3 c2 c6 c5 c1 c10 d4 d7 d8 d3 d2 d6 d5 d1 d10 e4 e7 e8 e9 e3 e2 e6 e5 e1 e10 f4 f7 f8 f9 f3 f2 f6 f5 f1 f10 g4 g7 g8 g9 g3 g2 g6 g1 g10 h4 h7 h8 h9 h3 h2 h1 h10 j4 j7 j8 j9 j3 j2 j6 j5 j1 j10 k4 k7 k8 k9 k3 k2 k6 k5 k1 k10 l4 l7 l8 l9 l3 l2 l6 l5 l1 l10 m4 m7 m8 m9 m3 m2 m6 m5 m1 m10 n4 n7 n8 n9 n3 n2 n6 n5 n1 n10 p4 p7 p8 p9 p3 p2 p6 p5 p1 p10 flash 1 only d-cke d-clk rfu rfu d-vss d-vcc d-a12 d-a11 d-vss d-ce# d-ras# d-we# d-a9 d-a8 d-vssq d-vccq d-a7 d-a6 rfu d-cas# d-a10 avd# vss clk rfu rfu rfu rfu rfu rfu d-a0 f-wp# a7 d-dm0 f-acc we# a8 a11 f2-ce# d-a5 d-vccq a3 a6 d-dm1 f-rst# rfu a19 a12 a15 d-vccq d-vssq a2 a5 a18 f-rdy a20 a9 a13 a21 d-vssq d-dq0 a1 a4 a17 a23 a10 a14 a22 d-dq15 d-dq1 a0 vss dq1 dq6 rfu a16 d-dq14 d-dq2 f1-ce# oe# dq9 dq3 dq4 dq13 dq15 rfu d-dq13 d-dq3 rfu dq0 dq10 f-vcc rfu dq12 dq7 vss d-dq12 d-dq4 rfu dq8 dq2 dq11 rfu dq5 dq14 rfu d-dq11 d-dq5 rfu rfu vss f-vcc rfu rfu rfu rfu d-dq10 rfu d-ba0 d-dq6 d-dq7 d-vssq d-vccq d-dq8 d-dq9 d-ba1 rfu rfu d-vss d-a1 d-a2 d-vss d-vcc d-a3 d-a4 rfu rfu flash 2 only flash shared d9 137-ball fine-pitch ball grid array (top view, balls facing down)
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 9 data sheet (advance information) 3.2 2 x 256mb nor flash with 128mb sdram note m8 is rfu for sdr-dram and f-vccq for ddr-dram, as indicated in subsequent connection diagrams. a1 a10 b4 b7 b8 b9 b3 b2 b6 a2 a3 a4 a5 a6 a7 a8 a9 b5 b1 b10 c4 c7 c8 c9 c3 c2 c6 c5 c1 c10 d4 d7 d8 d9 d3 d2 d6 d5 d1 d10 e4 e7 e8 e9 e3 e2 e6 e5 e1 e10 f4 f7 f8 f9 f3 f2 f6 f5 f1 f10 g4 g7 g8 g9 g3 g2 g6 g1 g10 h4 h7 h8 h9 h3 h2 h1 h10 j4 j7 j8 j9 j3 j2 j6 j5 j1 j10 k4 k7 k8 k9 k3 k2 k6 k5 k1 k10 l4 l7 l8 l9 l3 l2 l6 l5 l1 l10 m4 m7 m8 m9 m3 m2 m6 m5 m1 m10 n4 n7 n8 n9 n3 n2 n6 n5 n1 n10 p4 p7 p8 p9 p3 p2 p6 p5 p1 p10 d-cke d-clk rfu rfu d-vss d-vcc rfu d-a11 d-vss d-ce# d-ras# d-we# d-a9 d-a8 d-vssq d-vccq d-a7 d-a6 rfu d-cas# d-a10 avd# vss clk rfu rfu rfu rfu rfu rfu d-a0 f-wp# a7 d-dm0 f-acc we# a8 a11 f2-ce# d-a5 d-vccq a3 a6 d-dm1 f-rst# rfu a19 a12 a15 d-vccq d-vssq a2 a5 a18 f-rdy a20 a9 a13 a21 d-vssq d-dq0 a1 a4 a17 a23 a10 a14 a22 d-dq15 d-dq1 a0 vss dq1 dq6 rfu a16 d-dq14 d-dq2 f1-ce# oe# dq9 dq3 dq4 dq13 dq15 rfu d-dq13 d-dq3 rfu dq0 dq10 f-vcc rfu dq12 dq7 vss d-dq12 d-dq4 rfu dq8 dq2 dq11 rfu dq5 dq14 rfu d-dq11 d-dq5 rfu rfu vss f-vcc rfu rfu rfu rfu d-dq10 rfu d-ba0 d-dq6 d-dq7 d-vssq d-vccq d-dq8 d-dq9 d-ba1 rfu rfu d-vss d-a1 d-a2 d-vss d-vcc d-a3 d-a4 rfu rfu sdram only legend reserved fo r future use flash 1 only flash 2 only flash shared 137-ball fine-pitch ball grid array (top view, balls facing down)
10 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) 3.3 256mb nor flash wi th 128mb sdr/ddr-dram note ddr-only signals are rfus in the case of the sdr-dram based mcps. a1 a10 b4 b7 b8 b9 b3 b2 b6 a2 a3 a4 a5 a6 a7 a8 a9 b5 b1 b10 c4 c7 c8 c9 c3 c2 c6 c5 c1 c10 d4 d7 d8 d9 d3 d2 d6 d5 d1 d10 e4 e7 e8 e9 e3 e2 e6 e5 e1 e10 f4 f7 f8 f9 f3 f2 f6 f5 f1 f10 g4 g7 g8 g9 g3 g2 g6 g1 g10 h4 h7 h8 h9 h3 h2 h1 h10 j4 j7 j8 j9 j3 j2 j6 j5 j1 j10 k4 k7 k8 k9 k3 k2 k6 k5 k1 k10 l4 l7 l8 l9 l3 l2 l6 l5 l1 l10 m4 m7 m8 m9 m3 m2 m6 m5 m1 m10 n4 n7 n8 n9 n3 n2 n6 n5 n1 n10 p4 p7 p8 p9 p3 p2 p6 p5 p1 p10 d-cke d-clk d-clk# rfu d-vss d-vcc rfu d-a11 d-vss d-ce# d-ras# d-we# d-a9 d-a8 d-vssq d-vccq d-a7 d-a6 rfu d-cas# d-a10 avd# vss clk rfu rfu rfu rfu rfu rfu d-a0 f-wp# a7 d-dm0 f-acc we# a8 a11 rfu d-a5 d-vccq a3 a6 d-dm1 f-rst# rfu a19 a12 a15 d-vccq d-vssq a2 a5 a18 f-rdy a20 a9 a13 a21 d-vssq d-dq0 a1 a4 a17 a23 a10 a14 a22 d-dq15 d-dq1 a0 vss dq1 dq6 rfu a16 d-dq14 d-dq2 f1-ce# oe# dq9 dq3 dq4 dq13 dq15 rfu d-dq13 d-dq3 rfu dq0 dq10 f-vcc rfu dq12 dq7 vss d-dq12 d-dq4 rfu dq8 dq2 dq11 rfu dq5 dq14 rfu d-dq11 d-dq5 rfu rfu vss f-vcc rfu rfu f-vccq rfu d-dq10 rfu d-ba0 d-dq6 d-dq7 d-vssq d-vccq d-dq8 d-dq9 d-ba1 rfu d-dqs0 d-vss d-a1 d-a2 d-vss d-vcc d-a3 d-a4 rfu d-dqs1 sdram only legend reserved for future use flash 1 only flash 2 only flash shared ddr only 137-ball fine-pitch ball grid array (top view, balls facing down)
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 11 data sheet (advance information) 3.4 512 mb nor flash with 1024-mb o rnand on bus 1 and 512 or 256-mb sdram on bus 2 3.4.1 x16 ornand-based mcp note ddr-only signals are rfu in the case of sdr-dram based mcps. a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 g1 g2 g3 g4 g6 g7 g8 g9 g10 h1 h2 h3 h4 h7 h8 h9 h10 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 d-cke d-clk rfu d-v ss d-v cc d-a12 d-a11 d-v ss d-ce# d-ras# d-we# d-a9 d-a8 d-v ssq d-v ccq d-a7 d-a6 rfu d-cas# d-a10 avd# v ss clk f2-ce# f-v cc n-pre n-ale n-cle rfu d-a0 f-wp# a7 d-dm0 f-acc we# a8 a11 n-ce# d-a5 d-v ccq a3 a6 d-dm1 f-rst# dnu a19 a12 a15 d-v ccq d-v ssq a2 a5 a18 rdy a20 a9 a13 a21 d-v ssq d-dq15 a22 a14 a10 a23 a17 a4 a1 d-dq0 d-dq1 a0 vss dq1 dq6 rfu a16 d-dq14 d-dq13 dnu dq15 dq13 dq4 dq3 dq9 oe# f1-ce# d-dq2 d-dq3 dnu dq0 dq10 f-v cc n-v cc dq12 dq7 v ss d-dq12 d-dq11 n-wp# dq14 dq5 rfu dq11 dq2 dq8 n-vcc d-dq4 d-dq5 rfu rfu v ss f-v cc rfu dnu f-v ccq rfu d-dq10 n-re# d-ba1 d-dq9 d-dq8 d-v ccq d-v ssq d-dq7 d-dq6 d-ba0 n-we# rfu d-v ss d-a1 d-a2 d-v ss d-v cc d-a3 d-a4 n-ry/by# legend do not use nor flash 1 only nor flash 2 only nand flash 1 only reserved for future use dram only nor flash shared all flash shared rfu rfu b9 137-ball fine-pitch ball grid array (top view, balls facing down)
12 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) 3.5 512mb nor flash with 1024-mb ornand on bus 1 and 512 or 256 mb sdram on bus 2 3.5.1 x8 ornand-based mcp a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 g1 g2 g3 g4 g6 g7 g8 g9 g10 h1 h2 h3 h4 h7 h8 h9 h10 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 d-cke d-clk rfu rfu d-v ss d-v cc d-a12 d-a11 d-v ss d-ce# d-ras# d-we# d-a9 d-a8 d-v ssq d-v ccq d-a7 d-a6 rfu d-cas# d-a10 avd# v ss clk f2-ce# f-v cc n-pre n-ale n-cle rfu d-a0 f-wp# a7 d-dm0 f-acc we# a8 a11 n-ce# d-a5 d-v ccq a3 a6 d-dm1 f-rst# dnu a19 a12 a15 d-v ccq d-v ssq a2 a5 a18 rdy a20 a9 a13 a21 d-v ssq d-dq15 a22 a14 a10 a23 a17 a4 a1 d-dq0 d-dq1 a0 v ss dq1 dq6 rfu a16 d-dq14 d-dq13 dnu dq15 dq13 dq4 dq3 dq9 oe# f1-ce# d-dq2 d-dq3 dnu dq0 dq10 f-v cc n-v cc dq12 dq7 v ss d-dq12 d-dq11 n-wp# dq14 dq5 rfu dq11 dq2 dq8 n-vcc d-dq4 d-dq5 rfu rfu v ss f-v cc rfu dnu f-v ccq rfu d-dq10 n-re# d-ba1 d-dq9 d-dq8 d-v ccq d-v ssq d-dq7 d-dq6 d-ba0 n-we# rfu d-v ss d-a1 d-a2 d-v ss d-v cc d-a3 d-a4 dnu rfu legend do not use nor flash 1 only nor flash 2 only nand flash 1 only reserved for future use dram only nor flash shared all flash shared b9 137-ball fine-pitch ball grid array (top view, balls facing down)
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 13 data sheet (advance information) 3.6 512mb nor flash with 512-mb nand on bus 1 and 512-mb sdram on bus 2 3.6.1 x16 ornand-based mcp special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150 c for prolonged periods of time. a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 g1 g2 g3 g4 g6 g7 g8 g9 g10 h1 h2 h3 h4 h7 h8 h9 h10 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 d-cke d-clk rfu d-v ss d-v cc d-a12 d-a11 d-v ss d-ce# d-ras# d-we# d-a9 d-a8 d-v ssq d-v ccq d-a7 d-a6 rfu d-cas# d-a10 avd# v ss clk f2-ce# f-v cc n-pre n-ale n-cle rfu d-a0 f-wp# a7 d-dm0 f-acc we# a8 a11 n-ce# d-a5 d-v ccq a3 a6 d-dm1 f-rst# dnu a19 a12 a15 d-v ccq d-v ssq a2 a5 a18 rdy a20 a9 a13 a21 d-v ssq d-dq15 a22 a14 a10 a23 a17 a4 a1 d-dq0 d-dq1 a0 vss dq1 dq6 rfu a16 d-dq14 d-dq13 dnu dq15 dq13 dq4 dq3 dq9 oe# f1-ce# d-dq2 d-dq3 dnu dq0 dq10 f-v cc n-v cc dq12 dq7 v ss d-dq12 d-dq11 n-wp# dq14 dq5 rfu dq11 dq2 dq8 n-vcc d-dq4 d-dq5 rfu rfu v ss f-v cc rfu dnu f-v ccq rfu d-dq10 n-re# d-ba1 d-dq9 d-dq8 d-v ccq d-v ssq d-dq7 d-dq6 d-ba0 n-we# d-dqs0 d-v ss d-a1 d-a2 d-v ss d-v cc d-a3 d-a4 n-ry/by# legend do not use nor flash 1 only nor flash 2 only nand flash 1 only reserved for future use dram only nor flash shared all flash shared ddr only d-clk# d-dqs1 b9 137-ball fine-pitch ball grid array (top view, balls facing down)
14 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) 3.6.2 connection diagram for 15 x 15 package-on-package 3 4 5 6 7 8 9 10111213141516171819 c d e f g h j k l m n p r t u v w y 20 control for ddr, ps power ground b: addr a: a/d. b: data a: addr b: data legend f-rst# 21 22 f1-ce# n1-ce# rfu n-re# n-wp# f-we# f-wp# f-oe# f-v pp / n-acc 12 n-we# n-ry/by# d-dq14 f-adv# f-wait rfu f-clk rfu nc nc n-cle rfu n-ale rfu nc nc d-v dd a b aa ab no connect reserved for future use control for nor/ps/nand rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu f2-ce# d-dq15 d-dq13 d-dq12 d-dq11 d-dq10 d-dq9 d-dq8 d-dq7 d-dq6 d-dq5 d-dq4 d-dq3 d-dq2 d-dq1 d-dq0 f-a1 f-a2 f-a0 f-a3 f-a4 f-a5 f-a6 f-a7 f-a8 f-a9 f-a10 f-a11 f-a12 f-a13 f-a14 f-a15 f-a16 f-a17 f-a18 f-a19 f-a20 f-a21 f-a22 f-a23 f-dq14/ n-adq14 f-dq15/ n-adq15 f-dq12/ n-adq12 f-dq13/ n-adq13 f-dq10/ n-adq10 f-dq11/ n-adq11 f-dq8/ n-adq8 f-dq9/ n-adq9 f-dq6/ n-adq6 f-dq7/ n-adq7 f-dq4/ n-adq4 f-dq5/ n-adq5 f-dq2/ n-adq2 f-dq3/ n-adq3 f-dq0/ n-adq0 f-dq1/ n-adq1 d-a0 d-a1 d-a2 d-a3 d-a4 d-a5 d-a6 d-a7 d-a8 d-a9 d-a10 d-a11 d-a12 d-v ss d-v ss f-v ss f-v ssq f-v ssq n-v ss f-v ssq d-v ss d-v ss n-v ss f-v ssq f-v ssq f-v ssq f-v ssq f-v ssq f-v ss d-v ssq d-v ss d-v ssq d-v ssq d-v ssq f-v cc f-v ccq f-v ccq f-v ccq n-v cc d-v dd d-v dd f-v ccq f-v ccq f-v ccq n-v cc f-v cc f-v ccq f-v ccq d-v dd d-v ddq d-v dd d-v ddq d-v ddq d-v ddq d-we# d-ba0 d-ba1 d1-cs# d-ras# d-cas# d-cke d-clk d-clk# d-dm1 d-dqs1 d-dm0 d-dqs0
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 15 data sheet (advance information) 3.7 lookahead diagram on split bus a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 g1 g2 g3 g4 g6 g7 g8 g9 g10 h1 h2 h3 h4 h7 h8 h9 h10 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 d-cke d-clk d-clk# d-a14 d-v ss d-v cc d-a12 d-a11 d-v ss d-ce# d-ras# d-we# d-a9 d-a8 d-v ssq d-v ccq d-a7 d-a6 d-a13 d-cas# d-a10 f-avd# v ss f-clk f2-ce# f-v cc n-pre n-ale n-cle d-a15 d-a0 f-wp# a7 d-dm0 f-acc f-we# a8 a11 n1-ce# d-a5 d-v ccq a3 a6 d-dm1 f-rst# dnu a19 a12 a15 d-v ccq d-v ssq a2 a5 a18 f-rdy a20 a9 a13 a21 d-v ssq d-dq15 a22 a14 a10 a23 a17 a4 a1 d-dq0 d-dq1 a0 v ss dq1 dq6 a24 a16 d-dq14 d-dq13 dnu dq15 dq13 dq4 dq3 dq9 f-oe# f1-ce# d-dq2 d-dq3 dnu dq0 dq10 f-v cc n-v cc dq12 dq7 v ss d-dq12 d-dq11 n-wp# dq14 dq5 a25 dq11 dq2 dq8 n-v cc d-dq4 d-dq5 a27 a26 v ss f-v cc n2-ce# dnu f-v ccq d-clk# d-dq10 n-re# d-ba1 d-dq9 d-dq8 d-v ccq d-v ssq d-dq7 d-dq6 d-ba0 n-we# d-dqs0 d-v ss d-a1 d-a2 d-v ss d-v cc d-a3 d-a4 n-ry/by# d-dqs1 legend do not use nand flash x16 dram nor flash flash shared b9 ddr only
16 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) 3.8 nor flash and dram input/output descriptions 3.8.1 ornand sig nal descriptions signal description a23-a0 nor flash address inputs dq15-dq0 flash data input/output, shared between nor and ornand flash. dq0-dq7 shared for x8 ornand f2-ce# nor flash chip-enable input # 2. asynchronous relative to clk for burst mode. f1-ce# nor flash chip-enable input #1. asynch ronous relative to clk for burst mode. oe# nor flash output enable input. asynchronous relative to clk for burst mode. f-we# nor flash write enable input. f-v cc nor flash device power supply (1.7 v - 1.9 5 v). f-v cc q input/output buffer power supply. v ss ground rfu reserved for future use rdy flash ready output. indicates t he status of the burst read. v ol = data valid. shared between nor and ornand flash. clk nor flash clock. the first rising edge of clk in conjunct ion with avd# low latches the address input and activates burst mode operation. after the initial word is output, s ubsequent rising edges of clk increment the internal address counter. clk should remain low during asynchronous access. avd# nor flash address valid input. indicates to device that the valid address is present on the address inputs. v il = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of clk. v ih = device ignores address inputs f-rst# nor flash hardware reset input. v il = device resets and returns to reading array data f-wp# nor flash hardware write protect input. v il = disables program and erase functions in the four outermost sectors. f-acc nor flash accelerated input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. d-a12-d-a0 sdram address inputs d-dq15-d-dq0 sdram data input/output d-clk sdram system clock d-ce# sdram chip select d-cke sdram clock enable d-ba1-ba0 sdram bank select d-ras# sdram row address strobe d-cas# sdram column address strobe d-dm1-d-dm0 sdram data input/output mask d-we# sdram write enable input d-vss sdram ground d-vssq sdram input/output buffer ground d-vccq sdram input/output buffer power supply d-vcc sdram device power supply signal description n-pre ornand power-on read enable. tie to v ss on customer board if not used n-ale ornand address latch enable n-cle ornand command latch enable n-ce# ornand chip-enable n-wp# ornand write-protect n-we# ornand write-enable n-re# ornand read-enable n-ry/by# ornand ready-busy?this is shared with nor rdy n-i/o0-n-i/o15 ornand i/o signals (i/o0-i/o7 for x8 bus width) n-vcc ornand power supply
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 17 data sheet (advance information) 4. ordering information the order number is formed by a valid combinations of the following: 4.1 valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s72ws 512 n eg ba w 4 y 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number refer to the valid combinations tables package modifier refer to the valid combinations tables temperature range w = wireless (-25 c to +85 c) package type ba = very-thin fine-pitch bga lead (pb)-free compliant package bf = very-thin fine-pitch bga lead (pb)-free package kf = fine-pitch package-on-package (pop) lead (pb)-free sdram & data flash density ee = 256 mb sdram, 256 mb data flash de = 128 mb sdram, 256 mb data flash d0 = 128 mb sdram, no data flash fg = 512 mb sdram, 1024 mb ornand flash eg = 256 mb sdram, 1024 mb ornand flash ef = 256 mb sdram, 512mb nand flash ff = 512 mb sdram, 512mb nand flash process technology n = 110 nm, mirrorbit tm technology code flash density 256= 256mb 512= 512mb product family s72ws multi-chip product (mcp) 1.8-volt simultaneous read/write, burst mode flash memory and mobile sdram on split bus s72ws256nd0 valid combinations nor flash burst speed sdram supplier sdram burst speed package type package marking base ordering part number package & temperature model number packing type s72ws256nd0 bfw 93 0, 2, 3 (note 1) 66 mhz supplier 5 133 mhz 9x12x1.2mm 137- ball (note 2) l baw, bfw b7 54 mhz supplier 1 104 mhz bb supplier 2 kfw d3 66 mhz supplier 5 133 mhz 15x15x1.25mm 160- ball s72ws256nde valid combinations nor flash burst speed sdram supplier sdram burst speed package type package marking base ordering part number package & temperature model number packing type s72ws256nde baw, bfw u7 0, 2, 3 (note 1) 54 mhz supplier 1 104 mhz 9x12x1.4mm 137- ball (note 2) ub supplier 2
18 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) s72ws256nee valid combinations flash burst speed sdram supplier sdram burst speed package type package marking base ordering part number package & temperature model number packing type s72ws256nee baw, bfw u7 0, 2, 3 (note 1) 54 mhz supplier 1 104 mhz 9x12x1.4mm 137- ball (note 2) ub supplier 2 s72ws512nff valid combinations flash speed dram supplier dram speed package package marking base ordering part number package & temperature model number packing type s72ws512nff baw, bfw zj 0, 2, 3 (note 1) 66 mhz dram type 1 133 mhz 11 x 13 mm 137-ball (note 2) kfw 15 x 15 5mm 160-ball baw, bfw z2 dram type 5 11 x 13 mm 137-ball kfw 15 x 15 5mm 160-ball baw, bfw zt dram type 2 11 x 13 mm 137-ball kfw 15 x 15 5mm 160-ball s72ws512nfg valid combinations flash burst speed sdram supplier sdram burst speed package type package marking base ordering part number package & temperature model number packing type s72ws512nfg baw, bfw l7 0, 2, 3 (note 1) 54 mhz dram type 4 104 mhz 11x13x1.4mm 137- ball (note 2) l6 l5 47 46 45 lz dram type 2 ly lw 4z 4y 4w n7 dram type 4 n6 n5 67 66 65 nz dram type 2 ny nw 6z 6y 6w
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 19 data sheet (advance information) notes 1. packing type 0 is standard. sp ecify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. s72ws512neg valid combinations flash burst speed sdram supplier sdram burst speed package type package marking base ordering part number package & temperature model number packing type s72ws512neg baw, bfw lz 0, 2, 3 (note 1) 54 mhz dram type 2 104 mhz 11x13.1x1.4mm 137-ball (note 2) ly lw 4z 4y 4w nz ny nw 6z 6y 6w s72ws512nef valid combinations flash burst speed sdram supplier sdram burst speed package type package marking base ordering part number package & temperature model number packing type s72ws512nef kfw hj 0, 2, 3 (note 1) 66 mhz dram type 2 133 mhz 15x15x1.2 mm 160- ball (note 2)
20 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) 5. physical dimensions tld137?137-ball fine-pitch ball grid array (fbga) 12 x 9 mm package 3393\ 16-038.22a package tld 137 jedec n/a d x e 12.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 10.40 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 14 matrix size d direction me 10 matrix size e direction n 137 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement g5,h5,h6 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. pn ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 137x a1 a2 a 0.15 m c 0.08 m c ab pin a1
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 21 data sheet (advance information) fea137?137-ball fine-pitch ball grid array (fbga) 13 x 11 mm package 0.20 0.08 index mark 9 a a2 a1 corner pin a1 c 0.15 (2x) c b (2x) 0.15 c e d a m c c pn g sd 7 lk jh fedc a b ed 6 ee 3 1 2 4 5 8 7 9 10 d1 e1 se 7 6 137x b pin a1 corner bottom view top view side view 0.15 c a b m c m 0.08 max. 12.00mm x 9.00mm package 14 md ed sd/se ee b me n 0.80 bsc 0.40 bsc 0.80 bsc 0.40 10 d1 e d symbol a a1 a2 1.11 - min. 7.20 bsc 10.40 bsc 12.00 bsc 9.00 bsc - - - nom. 1.40 1.26 - package jedec fea 137 n/a matrix size d direction depopulated solder balls matrix size e direction solder ball placement ball pitch ball count ball pitch ball diameter note body thickness matrix footprint matrix footprint body size body size profile ball height d x e 1.37 0.35 0.45 g5, h5, h8 0.10 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means.
22 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) fvd137?137-ball fine-pitch ball grid array (fbga) 11 x 13 mm package 3522 \ 16-038.21 \ 09.29.05 package fvd 137 jedec n/a d x e 13.00 mm x 11.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.10 --- --- ball height a2 1.09 --- 1.24 body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 10.40 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 14 matrix size d direction me 10 matrix size e direction n 137 ball count ?b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd se 0.40 bsc. solder ball placement g5,h5,h6 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 0.08 c c 6 b 0.15 m c c ab m side view 137x 0.08 7 se e1 d1 10 9 8 6 4 5 2 1 3 ee 7 ed a corner pin a1 c d e f g h j k l m n 7 sd bottom view p c b a d e 0.15 (2x) c b c 0.15 (2x) 9 top view pin a1 corner a2 a index mark a1 0.20
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 23 data sheet (advance information) bwa160?160-ball fine-pitch ball grid array (fbga) 15 x 15 mm package 3518 \ 16-038.46 \ 02.23.06 package bwa 160 jedec n/a d x e 15.00 mm x 15.00 mm note package symbol min nom max a --- --- 1.25 profile a1 0.35 --- --- ball height a2 0.74 --- 0.84 body thickness d 15.00 bsc. body size e 15.00 bsc. body size d1 13.65 bsc. matrix footprint e1 13.65 bsc. matrix footprint md 22 matrix size d direction me 22 matrix size e direction n 160 ball count n 160 maximum number of balls r 2 number of land parameters ?b 0.40 0.45 0.50 ball diameter ee 0.65 bsc. ball pitch ed 0.65 bsc. ball pitch sd se 0.325 bsc. solder ball placement c3~c20,d3~d20,e3~e20,f3~f20 depopulated solder balls g3~g20,h3~h20,j3~j20,k3~k20 l3~l20,m3~m20,n3~n20,p3~p20 r3~r20,t3~t20,u3~u20,v3~v20 w3~w20,y3~y20 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10. outline and dimensions per customer requirement. y aa ab w 19 21 20 22 c c 0.20 0.10 c 6 b side view a2 a 160x a1 0.15 m c a b 0.08 m c a b 7 d f g e se c corner e1 h j m l k n p t r pin a1 d1 7 ee sd ed v 1 4 5 2 3 6 7 8 9 10 11 12 13 15 14 bottom view 17 18 16 u a d e index mark 9 corner pin a1 c b 0.10 (2x) top view c 0.10 (2x)
24 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) bwb160?160-ball fine-pitch ball grid array (fbga) 15 x 15 mm package package bwb 160 jedec n/a d x e 15.00 mm x 15.00 mm note package symbol min nom max a --- --- 1.30 profile a1 0.38 --- --- ball height a2 0.74 --- 0.84 body thickness d 15.00 bsc. body size e 15.00 bsc. body size d1 13.65 bsc. matrix footprint e1 13.65 bsc. matrix footprint md 22 matrix size d direction me 22 matrix size e direction n 160 ball count n 160 maximum number of balls r 2 number of land parameters ?b 0.43 0.48 0.53 ball diameter ee 0.65 bsc. ball pitch ed 0.65 bsc. ball pitch sd / se 0.325 bsc. solder ball placement depopulated solder balls 3523.3 \ 16-038.46 \ 5.7.7 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10. outline and dimensions per customer requirement.
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 25 data sheet (advance information) bta160?160-ball fine-pitch ball grid array (fbga) 15 x 15 mm package 3550 \ 16-038.55 \ 02.23.06 package bta 160 jedec n/a d x e 15.00 mm x 15.00 mm note package symbol min nom max a --- --- 1.30 profile a1 0.40 --- --- ball height a2 0.74 --- 0.84 body thickness d 15.00 bsc. body size e 15.00 bsc. body size d1 13.65 bsc. matrix footprint e1 13.65 bsc. matrix footprint md 22 matrix size d direction me 22 matrix size e direction n 160 ball count n 160 maximum number of balls r 2 number of land parameters ? b 0.45 0.50 0.55 ball diameter ee 0.65 bsc. ball pitch ed 0.65 bsc. ball pitch sd se 0.325 bsc. solder ball placement c3~c20,d3~d20,e3~e20,f3~f20 depopulated solder balls g3~g20,h3~h20,j3~j20,k3~k20 l3~l20,m3~m20,n3~n20,p3~p20 r3~r20,t3~t20,u3~u20,v3~v20 w3~w20,y3~y20 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10. outline and dimensions per customer requirement. 6 b side view c 160x 0.15 m c a b 0.08 m c a b 7 d e g h se f c corner k l n p m t u w y v r e1 j pin a1 d1 ee ed ab 1 3 4 2 5 6 7 8 7 sd 10 13 12 11 14 15 17 16 9 19 21 22 20 bottom view 18 aa a d e 9 corner pin a1 index mark c b 0.10 c 0.20 (2x) top view c 0.10 c 0.10 (2x) a1 a2 a
26 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) alh160?160-ball fine-pitch ball grid array (fbga) 15 x 15 mm package package alh 160 jedec n/a d x e 15.00 mm x 15.00 mm package symbol min nom max note a --- --- 1.10 profile a1 0.38 --- --- ball height a2 0.53 --- 0.65 body thickness d 15.00 bsc. body size e 15.00 bsc. body size d1 13.65 bsc. matrix footprint e1 13.65 bsc. matrix footprint md 22 matrix size d direction me 22 matrix size e direction n 160 ball count n 160 maximum number of balls r 2 number of land perimeters ?b 0.43 0.48 0.53 ball diameter ee 0.65 bsc. ball pitch ed 0.65 bsc ball pitch sd se 0.325 bsc. solder ball placement depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means.
may 8, 2007 s72ws-n_00_a9 s72ws-n based mcp/pop products 27 data sheet (advance information) 6. revision history section description revision a (august 26, 2004) initial release revision a 1 (june 1, 2005) global added sdram type 2 module added lead (pb)-free options added fea137 package diagram revision a2 (october 7, 2005) global updated the s29ws-n nor flash module added the s30ms-p ornand flash module added sdram type 4 module product selector guide updated the product selector guide connection diagrams added two diagrams for the x8 and x16 ornand connections pin descriptions updated descriptions and added descriptions for ornand signals ordering information added new options added package-on-package (pop) options valid combinations updated the valid combinations tables physical dimensions added the fga137 package diagram added the bwa160 package diagram added the bwb160 package diagram revision a3 (november 9, 2005) global updated the sdram type 1 module changed the status of all ram modules to preliminary from advanced. revision a4 (december 14, 2005) product selector guide updated the tables connection diagrams added the 512 mb nor flash with 512 mb nand on bus 1 and 512 mb sdram on bus 2 diagram ordering information added new model number, package modifier and sdram & data flash density options valid combinations updated all tables with new options revision a5 (december 16, 2005) connection diagrams updated the pinouts to include ddr signals qualified 133 mhz as ddr based frequency revision a6 (march 21, 2006) nor flash + ornand flash + dram mcps product selector guide updated the model numbers ordering information updated the table valid combinations updated the tables physical dimensions added the alh160 package revision a7 (april 18, 2006) connection diagrams updated the pinouts revision a8 (june 1, 2006) global added 2 opns for products with dram type 5 updated product selector guide updated valid combination table added bta160 package diagram revision a9 (may 8, 2007) physical dimensions added the alh 160 package diagram
28 s72ws-n based mcp/pop products s72ws-n_00_a9 may 8, 2007 data sheet (advance information) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004-2007 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , hd-sim ? and combinations thereof, are trademarks of spansion llc in the us and other countries . other names used are for informational purposes only and may be trademarks of their respective owners.

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